1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a bonding pad with low capacitance for a semiconductor device.
2. Description of the Related Art
Trends for electrical products are light, short, small, and thin. Usually, the chips manufacturing technology and the packaging technology are rapidly developed to meet these trends. However, due to a limitation of bonding machines, a size of a bonding pad for a semiconductor device is not reduced as well as a line width of a chip is greatly reduced. Because the size of the bonding pad is insufficiently small, an area of a substrate overlapped by the bonding pad is large. As a result, a parasitic capacitance of the bonding pad remains high. Additionally, a peel-off effect often occurs while forming the bonding wire, so that bonding reliability is decreased.
FIG. 1 is a cross-sectional view, schematically illustrating a conventional bonding pad.
Referring to FIG. 1, a dielectric layer 12 is formed on a substrate 10, and a metal layer 14 is formed on the dielectric layer 12. A passivation layer 16 having a bonding pad opening 18 is formed on the metal layer 14. A bonding pad wire 19 is formed on the metal layer 14 within the bonding pad opening 18. A parasitic capacitance of the bonding pad maybe small if the distance between the substrate 10 and the metal layer 14 is large. But if the bonding pad is only formed by the uppermost metal layer to increase the distance between the substrate 10 and the metal layer 14, the peel-off effect, denoted as a region 17, often occurs during formation of the bonding wire 19 and chip packaging. The bonding reliability is therefore reduced due to the peel-off effect.
The present invention provides a low-capacitance bonding pad for a semiconductor device so as to avoid a peel-off effect and reduce a parasitic capacitance of the bonding pad.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate at a region on which a bonding pad is to be formed. The bonding pad includes a stacked metal layer and a metal layer, in which the metal layer is on the stacked metal layer. The stacked metal layer includes several metal layers and several dielectric layers, in which the metal layers are isolated by the dielectric layers in between by alternately stacking them up. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with an adjacent metal layer by a via plug.
Since the bonding pad includes several metal layers and buried deeply in the dielectric layer, the peel-off effect is effectively avoided. An area of the substrate overlapped by the metal layers stacked in the stacked metal layer is small because the areas of the metal layers stacked in the stacked metal layer are small. As a result, the parasitic capacitance of the bonding pad is also effectively reduced. Moreover, the parasitic capacitance of the bonding pad is further reduced due to the diffusion region in the substrate, which serves as an additional capacitor coupled in series to the capacitor induced by the metal layers. The metal layers in the stacked metal layer can include various geometry structures. For example, the metal layer includes several metal bars in one layer and crosses to each other in different layer in different bar direction so as to form a geometric structure, such as a net structure or any other overlapping structure.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides another low-capacitance bonding pad for a semiconductor device. A device is formed under a bonding pad which is made from a stacked metal layer and an uppermost metal layer. The metal layers stacked in the stacked metal layer are formed with small area and each area of the metal layer in the stacked metal layer is smaller than the uppermost metal layer.
The device is formed on a substrate. Several metal layers close to the device serve as signal lines. Several metal layers stacked on the metal layers as signal lines serve as power lines, and other metal layers stacked on the power lines serve as the bonding pad which consists of a stacked metal layer and an uppermost metal layer. The metal layers in the stacked metal layer can include various geometry structures. For example, the metal layer includes several metal bars in one layer and crosses to each other in different layer in different bar direction so as to form a geometric structure, such as a net structure or any other overlapping structure.
Because the device is formed between the bonding pad and the substrate, an area of the integrated circuits layout is reduced. The area of the substrate overlapped by the metal layers stacked in the stacked metal layer is small since areas of the metal layers are small, so that the parasitic capacitance of the bonding pad is reduced. The peel-off effect is avoided and the bonding reliability increases because the bonding pad includes the stacked metal layers which are buried deeply in the dielectric layer.